How it is displayed depends on anycodings_python the user's locale.

anycodings_python The recorded thousands separator is a anycodings_python comma.

The clock frequency of the SineGen block is 1/100th of the Simulink System Period (or 1MHz for a 100MHz clock input).The thousands separator (and the decimal anycodings_python 'point' etc) are recorded in the XLS anycodings_python file in a locale-independent fashion. Let's use a simple model ( download the model for test1 here) below to show how all these periods play together in SysGen. Otherwise, Simulink will use the sample period of 1 for the DDS core and the output frequency will be wrong. IMPORTANT: if you set Simulink System Period to anything other than 1, 'Use explicit period' MUST be checked and 'Explicit Period' set to the same value as Simulink System period.

Explicit Sample Period: This is the sample period used for the DDS block.

DDS System Clock (Mhz) = 1/FPGA clock period). Set it to match the FPGA clock period (i.e.

DDS System Clock (Mhz): It's used to calculate the phase increment for DDS block (see the DDS datasheet for details).

Usually it is set to 1 to keep everything simple. There is no significance in its absolute value as long as the sampling periods of all other blocks are multiple of the Simulink System Period. This is the lowest sampling period (highest sampling frequency) among all blocks in the model.

Simulink System Period: only used in Simulink simulation.

it will NOT affect output frequency of the DDS block). This value does NOT affect simulation in Simulink (i.e. FPGA clock period (ns): only used for FPGA synthesis and implementation.

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